This invention relates to a read only memory device (ROM), and in particularly to an electrically erasable and programmable read only memory (EEPROM) device having a more compact size and higher programming speed than a conventional EEPROM device.
EEPROM devices, in general, and methods for making such devices, are well known in the art. Typically, an EEPROM device structure has a floating gate and a control gate, both of which are typically fabricated out of polycrystalline silicon doped with an appropriate doping material to render the polycrystalline conductive. A typical doping material is phosphorous.
The floating gate is separated from a substrate region by a gate dielectric layer of insulating material such as silicon dioxide, while the substrate region includes source and drain regions with a channel region therebetween. The floating gate and the control gate are separated by an intergate dielectric, typically silicon dioxide. The basic principle upon which the EEPROM device operates is as follows: the charge is stored on the floating gate in a capacitive manner and can be subsequently electrically erased as described in U.S. Pat. No. 5,146,426 herein incorporated by reference.
There are many different trench-based EEPROM device structures, such as the one described in Japanese Patent No. 3-280580, which shows a memory cell consisting of two transistors in series. One side of the trench is a stacked-gate MOSFET. The other side of the trench is a single gate MOSFET. The gate structures are separated from each other at the bottom of the trench.
Japanese Patent No. 1-81368 shows an EEPROM device where the channel region is on the top surface of the substrate and only the tunnel oxide and first polysilicon layer extending into the trench. The inter-poly layer and second polysilicon layer are disposed outside the trench.
Another embodiment is shown in U.S. Pat. No. 4,990,979 which shows a trench-based EEPROM device wherein two memory cells share a single trench. In addition, the channel region is on the top surface of the substrate and the gate oxide and tunnel oxide layers are separately formed.
In order to overcome the disadvantages of earlier trench-based EEPROM devices, a compact EEPROM device, such as the one described in U.S. Pat. No. 5,146,426, includes an insulated control gate and an insulated floating gate formed in a trench within a semiconductor body. A surface-adjoining drain region is provided alongside an upper portion of a sidewall of the trench, while a source region is provided alongside the lower portion of the sidewall of the trench, with a channel region extending along the sidewall of the trench between the source and drain regions. The device is programmed through the trench sidewall portion which is adjacent the channel region, and is erased through a corner region in the bottom of the trench by causing a localized high electric field density in the corner region during the erase operation.
As the use of EEPROM devices continues to grow, it is important that the programming speed be increased beyond that of a conventional EEPROM device. None of these EEPROM devices offers a significantly high programming speed while maintaining the trench-based configuration.